I have been doing timing gate level simulations recently.
There are several reason why we do gate level simulations but my purpose of the activity was to generate vcd snapshots to capture transition activity on the design in order to calculate the IR drop.
Some of the open points are/were:
1) What is IR drop calculation? Why is it done?A: Power is supplied to the design through power grids or bumps. The purpose of the IR Drop activity is to calculate the max voltage drop area in the design and to see if this maximum drop is within the acceptable limits.
2) What is the role of vcds for IR Drop?
A: vcd is a capture of the real toggling activity on the design in terms of ports and internal signals.With the help of libraries,netlist and contraints , this can be mapped to real activies on the design.
3) Which test is best suited for vcd cut for IR drop?
A: The test which has transition from max to min activities or the reverse should be best suited for IRDrop
Inputs required:
1) netlist : A backend netlist.2) sdf: A file which contains all the net delays in the design.An sdf has 3 kinds of delay for each net as <min:typ:max> (not sure of the order). The choice of delay is chosen by the parameter MTM_CONTROL in ncsim. The relationship is as follows:
| Condition | MTM_CONTROL |
| Best | Minimum |
| Worst | Maximum |
| Typical | Typical |
Each entry is of the form:
PATH full_hierarchical_path -tcheck4) no reset flop list : To deposit either 1 or 0 to outputs of these flops to avoid ‘X’ propagation in the design during simulation. Since we get only the list of flops from synthesis guys, we assume the flops have both Q and QN pins and deposit 1′b0 and 1′b1 respectively.
This should also be achieved by flag NC_INITIALIZE during elaboration which also serves the same purpose but i observed that this flag didn’t work for me. I saw some ‘X’ propagation even after using this flag so i safely used the no rst file.
Each entry is of the form:
deposit full_hierarchical_path.Q - 1'b0 -relative
Take Care
1. Enable timing checks during elaboration. In ncsim, its done by not including the switch -NoTimingChecks in ncelab.2. Compile all the netlists and library RTL without the -functional switch defined otherwise “no-timing” code will be compiled.
Setup Issues
There could be several setup issues encountered while setting up a gate level simulation environment.
1) Setup/Hold violations : There could be several setup/hold violations during the simulation. Please go ahead and debug the first violation. It will give an idea if the environment is properly set up. Please check if :
- Your sdf is properly annotated and there are no errors/warnings which are terminating the annotation process prematurely. This could lead to wrong delays in the design and thus wrong timing violations during simulations.
- The Pins that are driven directly by the testbench might cause a timing violation on the first encountered flop in the design as your testbench might be using the same clock to generate the data which is used to capture the data in the design. In this case since the testbench in pure RTL. Its delay is zero and thus first flop might face a unwanted timing violations sue to clock skew and data delay. Such violations are wrong and can be avoided by delaying the input w.r.t the clock.
- timescale directive is properly set according to delays mentioned in your files.
- Any timing violation that occurs before the design comes out of reset should be safely ignored.
- All your non resettable flops are properly initialized to either 1′b0 and 1′b1. The list of non resettable flops is complete.
Please note although , gate level simulations take a lot of real time compare to RTL simulation, the time intervals in the test is the same. It means a test which takes X ns in RTL simulation will take the same amount in Gate level simulations too.
