CDC pitfall - Unsync static signal in a state machine

We all know  Clock Domain Crossing(CDC) can bite you in various ways. This post discuss one such way, to serve just as a reminder of how a simple and seemingly harmless things can cause a big damage.

A signal originating from one clock domain and used in another domain without proper synchronization can cause problems in various ways. But a common notion is that a signal whose timing is not critical is usually harmless from this phenomenon.For example signals coming from the register programming interface. That is why while analyzing the CDC check report, sometimes we ignore the static signal and are tempted to mark then as "quasi static" to ignore the checks on them as they seem harmless.This is okay for some of the cases , only if you are lucky :-)

What really happens when you are really lucky

If a static signal A is originated from clock domain clk_A and used in clock domain clk_B without any synchronization, The worst thing that can happen here is that the first flop(in clk domain B) which captures this data, could go into metastable state, but assuming the MTBF requirements are met , the next flop will always capture a stable value and cannot go into metastable state. So even if there are combinational logic between the first and second flop, STA makes sure that all the timing requirements are met therefore

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Signal A being a static signal , it doesn't matter if Flop B settles to a wrong value after going into metastable state, the correct value will come in the next cycle and everything will work as it should.


What happens when you are not (lucky)

If the Signal coming from a different domain, instead of hitting a flop directly in the destination domain, goes through a logic or particularly a state machine which is written in the following way.
Here we are discussing one very specific case. 
cfg_static_setting_a is the configuration static signal coming from a different domain and use directly here into a different domain, without proper synchronization.

module (
input clk,
input rst_n,
input cfg_static_setting_a,
....
)

//One hot decoding of state vector
localparam IDLE         = 3'b001;
localparam STATE_X = 3'b010;
localparam STATE_Y = 3'b100;

//Combo logic
always @* begin
   nxt_state = state;
   case(state)
   IDLE:  begin
              if (cfg_static_setting_a) 
                     .... 
                     nxt_state = STATE_X;
                     ....
   end
   STATE_X: ...
   STATE_Y: ...
   endcase
end

// Seq logic
always @(posedge clk or negedge rst_n)begin
   if(~rst_n)begin
           nxt_state <= IDLE;
   end
   else begin
           state <= nxt_state;
   end
end

endmodule


Since this signal directly governs the state flops, and state flops are coded as one hot vector.
What might happen here is that a Metastable glitch can cause the state vector to change in a fashion that they take a completely invalid value - say 3'b000 and in the absence of any default condition, this state machine will be stuck in an unknown state forever and will never recover. This is fatal...

Learning...
Therefore

• Any signal coming from a different domain must atleast be registered once in the destination domain if not synchronized properly.
• It is a good practice to always have a default state in your state machine to atleast assign the state signal to a known state such as IDLE.  

Counting "Ones"...

Finding the number of  '1' in a binary sequence is useful. Many operations require you to create a sequence within a structure to indicate an event. For example, if the application is receiving event requests from multiple places which is getting collected in a 32 bit vector(a[32]) and at any point, it is to be determined that how many such events have occurred. The crude way of doing so is to loop through the complete vector and count the number of '1'

for(i=0;i<=32;i=i+1)

{

 if(a[i]==1)

   count= count+1;

}

This takes as much as the size of the array(32 in this case) to complete the calculations but is a nice and simple method.

If number of iterations is of importance, then there ought to be methods which only takes as many iterations as there are actual number of '1's in the number. I came across one such method and how it works amaze me because i didn't know there exist a correlation between a binary number and its successor or predecessor in binary. I need to find the proof of this method. The method simply goes like the following.

x=a;

for(count=0;x!=0;x=x&(x-1))

count = count +1;

Find proof of this?

I found this is a very famous "Brian Kernighan Algorithm" 

DISABLE IMPLICIT DECLARATION OF WIRES in Verilog

As you might know, since verilog 2001, wires are implicitly declared in verilog.That means you can start using a net in verilog and assume as if you declared it as a single bit wire. The important thing to notice here is that as long as you use it as a single bit wire, you are safe.
If verilog was "C" , i would have appreciated this feature or called it as an "enhancement".

But it is not. Verilog is meant to write RTLs. While writing RTL, the more you are forced to be specific ,the lesser error prone you are making the environment.

Let me give you an example ,how it can screw you.

wire psel;

abc u_abc(
.PSEL(pselx),
...
)

xyz u_xyz(
.PSEL_SOC(psel),
...
)

SEE!!!

Lets say you meant to connect PSEL of module abc with PSEL_SOC of module xyz through a wire psel.
Now instead of connecting the PSEL of module abc with previously declared wire psel, you connected it with pselx (because you were using gvim and x is frequently used to delete items :)

Now since pselx is not a declared wire, you would have preferred verilog throwing an error but it declared pselx as an implicit declaration of the wire and carried on.
Result: Your connection remains floating, a BUG is born.

I have encountered this scenario today. and i thought there must be some way to disable this "feature" either in the compiler or in the language and this is what i found.

There is a compiler directive as

`default_nettype none

When used in a verilog file, will stop defining any undeclared net implicitly.

NICE.

Line Debugging in Simulation

There was time when during my functional simulation, the simulator hangs at one point and does't advance. I have seen times during simulations when the time advances but nothing comes up or changes in the waveform. That happens because your design (or processor in my case) is stuck at some point like a WFI or bus-hang kind of situations but this was different. This was the time when the time in the simulation didn't advance at all.This was something new for me. I didnt know how to debug the situation or to know what part of verilog code was causing the issue.After spending some time with the issue, i came across the term "line debugging". I had heard the term with respect to C/C++ where GDB serves the same purpose just didnt know it existed for verilog simulation too. So here is how it is done for ncsim simulation(i am sure similar options exists for all other simulators):


1.Compile your code with -LINEDEBUG option in both ncverilg and ncvhdl command lines.
2.Then when the simulator hangs,hit CTRL-C on the console window
3.Type "run -step" on console and open source browser.
4.Continue running "run -step " . You see a yellow line moves on the source code indicating what part of RTL is being executed.
5.Continue running until you figure out you have been here before :-)

This way you can easily find the piece of code which may cause a loop back. In my case that piece of code looked something like this:

always @* begin
a <= a|b;
end

With the presence of * for sensitivity list, both a and b comes under it. so whenever there is an event on a or b, the block gets executed which might cause a change in a again. This is a combinational loop in the design and is forbidden.

-linedebug option i found out later causes to slow down the simulation time a lot and hence should not be used unless you are line debugging.


Happy debugging!!!

Gate Level Simulations

I have been doing timing gate level simulations recently.
There are several reason why we do gate level simulations but my purpose of the activity was to generate vcd snapshots to capture transition activity on the design in order to calculate the IR drop.

Some of the open points are/were:

1) What is IR drop calculation? Why is it done?
A: Power is supplied to the design through power grids or bumps. The purpose of the IR Drop activity is to calculate the max voltage drop area in the design and to see if this maximum drop is within the acceptable limits.
2) What is the role of vcds for IR Drop?
A: vcd is a capture of the real toggling activity on the design in terms of ports and internal signals.With the help of libraries,netlist and contraints , this can be mapped to real activies on the design.
3) Which test is best suited for vcd cut for IR drop?
A: The test which has transition from max to min activities or the reverse should be best suited for IRDrop

Inputs required:

1) netlist : A backend netlist.
2) sdf: A file which contains all the net delays in the design.An sdf has 3 kinds of delay for each net as  <min:typ:max> (not sure of the order). The choice of delay is chosen by the parameter MTM_CONTROL in ncsim. The relationship is as follows:

Condition	MTM_CONTROL
Best	Minimum
Worst	Maximum
Typical	Typical

3) tcheck file : A file containing a list of all the first flops of the synchronizes in the design where a timing violation is guaranteed and thus taken cared of by the design such as placing synchronizers.Therefore we dont check timing violations in this path.
Each entry is of the form:

 PATH full_hierarchical_path -tcheck

4) no reset flop list : To deposit either 1 or 0 to outputs of these flops to avoid ‘X’ propagation in the design during simulation. Since we get only the list of flops from synthesis guys, we assume the flops have both Q and QN pins and deposit 1′b0 and 1′b1 respectively.
This should also be achieved by flag NC_INITIALIZE during elaboration which also serves the same purpose but i observed that this flag didn’t work for me. I saw some ‘X’ propagation even after using this flag so i safely used the no rst file.
Each entry is of the form:

 deposit full_hierarchical_path.Q - 1'b0 -relative 

Take Care

1. Enable timing checks during elaboration. In ncsim, its done by not including the switch -NoTimingChecks in ncelab.
2. Compile all the netlists and library RTL without the -functional switch defined otherwise “no-timing” code will be compiled.

Setup Issues

There could be several setup issues encountered while setting up a gate level simulation environment.
1) Setup/Hold violations : There could be several setup/hold violations during the simulation. Please go ahead and debug the first violation. It will give an idea if the environment is properly set up. Please check if :

• Your sdf is properly annotated and there are no errors/warnings which are terminating the annotation process prematurely. This could lead to wrong delays in the design and thus wrong timing violations during simulations.
• The Pins that are driven directly by the testbench might cause a timing violation on the first encountered flop in the design as your testbench might be using the same clock to generate the data which is used to capture the data in the design. In this case since the testbench in pure RTL. Its delay is zero and thus first flop might face a unwanted timing violations sue to clock skew and data delay. Such violations are wrong and can be avoided by delaying the input w.r.t the clock.
• timescale directive is properly set according to delays mentioned in your files.
• Any timing violation that occurs before the design comes out of reset should be safely ignored.

2) ‘X’ propagation : If you see no timing violations and still see an X propagation in the design, Please check if:

• All your non resettable flops are properly initialized to either 1′b0 and 1′b1. The list of non resettable flops is complete.

Please note although , gate level simulations take a lot of real time compare to RTL simulation, the time intervals in the test is the same. It means a test which takes X ns in RTL simulation will take the same amount in Gate level simulations too.

The Purpose

How many times have you LEARNT something new ,then forgot about it completely and then went ahead and re-LEARNT the whole thing again only to forget it again.

My point exactly..


I hope i be able to update this often enough and it serves as knowledge database for me and for anyone who finds it. :-)