We all know Clock Domain Crossing(CDC) can bite you in various ways. This post discuss one such way, to serve just as a reminder of how a simple and seemingly harmless things can cause a big damage.
A signal originating from one clock domain and used in another domain without proper synchronization can cause problems in various ways. But a common notion is that a signal whose timing is not critical is usually harmless from this phenomenon.For example signals coming from the register programming interface. That is why while analyzing the CDC check report, sometimes we ignore the static signal and are tempted to mark then as "quasi static" to ignore the checks on them as they seem harmless.This is okay for some of the cases , only if you are lucky :-)
What really happens when you are really lucky
If a static signal A is originated from clock domain clk_A and used in clock domain clk_B without any synchronization, The worst thing that can happen here is that the first flop(in clk domain B) which captures this data, could go into metastable state, but assuming the MTBF requirements are met , the next flop will always capture a stable value and cannot go into metastable state. So even if there are combinational logic between the first and second flop, STA makes sure that all the timing requirements are met therefore
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Signal A being a static signal , it doesn't matter if Flop B settles to a wrong value after going into metastable state, the correct value will come in the next cycle and everything will work as it should.
What happens when you are not (lucky)
If the Signal coming from a different domain, instead of hitting a flop directly in the destination domain, goes through a logic or particularly a state machine which is written in the following way.
Here we are discussing one very specific case.
cfg_static_setting_a is the configuration static signal coming from a different domain and use directly here into a different domain, without proper synchronization.
module (
input clk,
input rst_n,
input cfg_static_setting_a,
....
)
//One hot decoding of state vector
localparam IDLE = 3'b001;
localparam STATE_X = 3'b010;
localparam STATE_Y = 3'b100;
//Combo logic
always @* begin
nxt_state = state;
case(state)
IDLE: begin
if (cfg_static_setting_a)
....
nxt_state = STATE_X;
....
end
STATE_X: ...
STATE_Y: ...
endcase
end
// Seq logic
always @(posedge clk or negedge rst_n)begin
if(~rst_n)begin
nxt_state <= IDLE;
end
else begin
state <= nxt_state;
end
end
endmodule
Since this signal directly governs the state flops, and state flops are coded as one hot vector.
What might happen here is that a Metastable glitch can cause the state vector to change in a fashion that they take a completely invalid value - say 3'b000 and in the absence of any default condition, this state machine will be stuck in an unknown state forever and will never recover. This is fatal...
Learning...
Therefore
- Any signal coming from a different domain must atleast be registered once in the destination domain if not synchronized properly.
- It is a good practice to always have a default state in your state machine to atleast assign the state signal to a known state such as IDLE.
