As you might know, since verilog 2001, wires are implicitly declared in verilog.That means you can start using a net in verilog and assume as if you declared it as a single bit wire. The important thing to notice here is that as long as you use it as a single bit wire, you are safe.
If verilog was "C" , i would have appreciated this feature or called it as an "enhancement".
But it is not. Verilog is meant to write RTLs. While writing RTL, the more you are forced to be specific ,the lesser error prone you are making the environment.
Let me give you an example ,how it can screw you.
wire psel;
abc u_abc(
.PSEL(pselx),
...
)
xyz u_xyz(
.PSEL_SOC(psel),
...
)
SEE!!!
Lets say you meant to connect PSEL of module abc with PSEL_SOC of module xyz through a wire psel.
Now instead of connecting the PSEL of module abc with previously declared wire psel, you connected it with pselx (because you were using gvim and x is frequently used to delete items :)
Now since pselx is not a declared wire, you would have preferred verilog throwing an error but it declared pselx as an implicit declaration of the wire and carried on.
Result: Your connection remains floating, a BUG is born.
I have encountered this scenario today. and i thought there must be some way to disable this "feature" either in the compiler or in the language and this is what i found.
There is a compiler directive as
`default_nettype none
When used in a verilog file, will stop defining any undeclared net implicitly.
NICE.
It did not help me...
ReplyDelete`default_nettype none
module x;
a a_inst( .w(someWire) );
wire someWire;
b b_inst( .w(someWire) );
...
resulted in an error that b.w is not connected. So the default_nettype setting is fooled by the wire declaration, but it actually overwrites an implicit wire. I think this has something to do with some ancient code from the Vivado parser.
Verilator does not catch the problem either...
Once the wire is declared, the default_nettype has no meaning to that wire.
ReplyDeleteVivado removes any unconnected wires before making this check, so this suggests both .w ports are inputs. In this case, the message really means nothing is driving the wire.
ReplyDelete